Semiconductor Device and Method for Manufacturing the Same

ABSTRACT

A semiconductor device and a method for manufacturing the same are provided. An n-well region can be formed on a semiconductor substrate, and a base contact region can be formed on the n-well region. An emitter contact region, a collector contact region, and a p-base region can also be formed on the n-well. The emitter and collector contact regions can include n-type ions, and the base contact region and the p-base region can include p-type ions. Thus, the semiconductor device can include an n-channel metal oxide semiconductor transistor and an NPN bipolar transistor.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims the benefit under 35 U.S.C. §119 ofKorean Patent Application No. 10-2007-0135957, filed Dec. 22, 2007,which is hereby incorporated by reference in its entirety.

BACKGROUND

A bipolar transistor, a type of semiconductor integrated device, is asemiconductor device with two PN junctions formed with a base, acollector, and an emitter on a silicon substrate. A bipolar transistorgenerally performs switching and amplification functions.

A bipolar transistor is typically configured with the collectorenclosing the perimeter of the emitter, so that current flows from theemitter past the base to the collector. Additionally, the base has adopant with a polarity different from that of a dopant of the emitterand collector. The resistance of the base can be selectively changed tocontrol current flowing from the emitter to the collector.

BRIEF SUMMARY

Embodiments of the present invention provide semiconductor devices withfavorable electrical characteristics and methods for forming thesemiconductor devices. According to embodiments, an NPN bipolar trenchcan be formed in a complementary metal oxide semiconductor (CMOS)device.

In one embodiment, a semiconductor device can include: a semiconductorsubstrate including an n-well; an n-channel metal oxide semiconductor(NMOS) transistor on the semiconductor substrate separated from then-well by a device isolation layer; a p-base region on the n-well; abase contact region and an emitter contact region on the p-base region;and a collector region on the n-well; wherein the emitter contact regioncomprises n-type ions, and wherein the collector contact regioncomprises n-type ions, and wherein the base contact region comprisesp-type ions, and wherein the p-base region comprises p-type ions.

In another embodiment, a method for manufacturing a semiconductor devicecan include: forming an n-well region on a semiconductor substrate;forming a gate on the semiconductor substrate separated from the n-wellregion by a device isolation layer; forming a base contact region on then-well region; forming a source region and a drain region for the gateon the semiconductor substrate; forming an emitter contact region and acollector contact region on the n-well; and forming a p-base region onthe n-well including on the base contact region and the emitter contactregion; wherein the source region comprises n-type ions, and wherein thedrain region comprises n-type ions, and wherein the emitter contactregion comprises n-type ions, and wherein the collector contact regioncomprises n-type ions, and wherein the base contact region comprisesp-type ions, and wherein the p-base region comprises p-type ions.

The details of one or more embodiments are set forth in the accompanyingdrawings and the description below. Other features will be apparent fromthe detailed description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 6 are cross-sectional views showing methods for manufacturingsemiconductor devices according to embodiments of the present invention.

DETAILED DESCRIPTION

Reference will now be made in detail to the embodiments of the presentdisclosure, examples of which are illustrated in the accompanyingdrawings.

When the terms “on” or “over” are used herein, when referring to layers,regions, patterns, or structures, it is understood that the layer,region, pattern, or structure can be directly on another layer orstructure, or intervening layers, regions, patterns, or structures mayalso be present. When the terms “under” or “below” are used herein, whenreferring to layers, regions, patterns, or structures, it is understoodthat the layer, region, pattern, or structure can be directly under theother layer or structure, or intervening layers, regions, patterns, orstructures may also be present.

FIG. 6 is a cross-sectional view of a semiconductor device according toan embodiment of the present invention.

Referring to FIG. 6, a semiconductor device according to an embodimentcan include a semiconductor substrate 10 with an n-well 20 and a deviceisolation layer 5; an n-channel metal oxide semiconductor (nMOS)transistor 35 including a source and a drain region 30 and a gate 15formed on the semiconductor substrate 10; a base contact region 40, anemitter contact region 50, and a collector contact region 60 formed onthe n-well 20; and a p-base region 70 formed on the n-well 20.

The semiconductor substrate 10 can be formed of, for example, a p-typesilicon substrate, and the semiconductor substrate 10 can includeadditional layers, such as an epitaxial layer.

In an embodiment, an interlayer dielectric 80 including contacts 85 canbe formed on the semiconductor substrate 10 including the nMOStransistor 35 and the NPN bipolar transistor 100. The contacts 85 can berespectively connected to the source and drain regions 30, the basecontact region 40, the emitter contact region 50, and the collectorcontact region 60.

A thermal oxide layer 2 can be formed between the device isolation layer5 and the semiconductor substrate 10.

The thermal oxide layer 2 can be formed to improve interfacialcharacteristics between the semiconductor substrate 10 and thedielectric of the device isolation layer 5.

The base contact region 40 and the emitter contact region 50 can beprovided in the p-base region. The p-base region 70 can be formed on then-well 20.

In an embodiment, the source and drain regions 30, the emitter contactregion 50, and the collector contact region 60 can be formed with n-typeions, and the base contact region 40 and the p-base region 70 can beformed with p-type ions.

According to embodiments, the emitter contact region 50, the p-baseregion 70, and the n-well 20 form an NPN bipolar transistor 100.

Additionally, the p-base region 70 can be formed with p-type ions at alow concentration, and the base contact region 40 can be formed with aconcentration of p-type ions higher than that of the p-base region 70(i.e. at a high concentration).

FIGS. 1 to 6 are cross-sectional views showing methods for manufacturingsemiconductor devices according to embodiments of the present invention.

Referring to FIG. 1, an n-well 20 and a device isolation layer 5 can beformed on a semiconductor substrate 10.

In an embodiment, the device isolation layer 5 can be formed on thesemiconductor substrate 10 and separating a first region (A) from asecond region (B), and the n-well 20 can be formed on the second region(B) of the semiconductor substrate 10

The n-well 20 can be formed through any suitable process known in theart. For example, a first photoresist pattern can be formed on the firstregion (A), and a first ion implantation can be performed to form then-well 20. The ions for the first ion implantation can be any suitableions known in the art, for example, phosphorous (P) ions.

The first region (A) can be a region for forming an nMOS transistor, andthe second region (B) can be a region for forming an NPN bipolartransistor.

The semiconductor substrate 10 can be formed of, for example, a p-typesilicon substrate, and the semiconductor substrate 10 can includeadditional layers, such as an epitaxial layer.

Also, a first heat treating process can be performed on thesemiconductor substrate 10 including the n-well 20 to activate ionsimplanted in the n-well 20.

During the first heat treating process, the ions implanted in the n-well20 can be activated and any defects that may be present on thesemiconductor substrate 10 can be repaired.

The device isolation layer 5 can be formed by patterning a trench in thesemiconductor substrate 10. Then, a thermal oxide layer 2 can be formedin the trench, and the trench can be filled with a dielectric.

The thermal oxide layer 2 can be formed to improve interfacialcharacteristics between the semiconductor substrate 10 and thedielectric. However, in certain embodiments, the thermal oxide layer 2may be omitted.

Referring to FIG. 2, a gate 15 can be formed on the semiconductorsubstrate 10 in the first region (A).

The gate 15 can be formed through any suitable process known in the art.For example, the gate can be formed of a first oxide layer pattern, apolysilicon pattern, and a spacer. A first oxide layer and a polysiliconlayer can be formed on the semiconductor substrate 10 and patterned toform the first oxide layer pattern and the polysilicon pattern,respectively. In one embodiment, the spacer can be anoxide-nitride-oxide spacer. For example, an oxide-nitride-oxide (ONO)layer can be formed on the semiconductor substrate 10 including thefirst oxide layer pattern and the polysilicon pattern, and anisotropicetching can be performed to form the spacer. Embodiments of the spacerare not limited to the ONO structure, and can have, for example, anoxide-nitride (ON) structure.

Also, while not shown in the Figures, before the spacer is formed, alightly doped drain (LDD) region can be formed on the semiconductorsubstrate 10 including the gate 15, to inhibit leakage of channelcurrent.

Referring to FIG. 3A, a second photoresist pattern 200 can be formed onthe semiconductor substrate 10, and a second ion implantation can beperformed to form a base contact region 40.

The base contact region 40 can be formed with, for example, a p-typeion.

The second ion implantation process can be performed using any suitableion known in the art, for example, boron.

The base contact region 40 can be formed on the n-well 20 formed in thesecond region (B).

Referring to FIG. 3B, in one embodiment, the base contact region 40, canbe simultaneously formed with source and drain regions 45 of a pMOS gate17 formed on a third region (C). Thus, a separate mask would not berequired during the second ion implantation when fabricating CMOStransistors.

Next, referring to FIG. 4, a third photoresist pattern 300 can be formedon the semiconductor substrate 10, and a third ion implantation processcan be performed to form an emitter contact region 50 and a collectorcontact region 60 in the second region (B) and source/drain regions 30in the first region (A).

In an embodiment, the third ion implantation process can be performed tosimultaneously form the source/drain regions 30, the emitter contactregion 50, and the collector contact region 60. Thus, a separate maskwould not be required during the third ion implantation.

The third ion implantation process can be performed using any suitableions known in the art, for example, phosphorous (P) ions.

The source and drain regions 30, along with the gate 15 can form thenMOS transistor 35.

Also, the emitter contact region 50 and collector contact region 60 canbe formed on the n-well 20 in the second region (B).

Referring to FIG. 5, a fourth photoresist pattern 400 can be formed onthe semiconductor substrate 10, and a fourth ion implantation processcan be performed to form a p-base region 70 in the n-well 20.

The fourth ion implantation process can be performed using any suitableions known in the art, for example, boron ions. Also, the p-base region70 can be lightly doped with p-type ions at a shallow depth, to helpincrease current gain.

While the depth of the p-base region 70 can be shallow, it can still bedeeper than that of the emitter contact region 50 and the base contactregion 40.

Also, in an embodiment, the base contact region 40 can be doped with ahigher concentration of ions than the p-base region 70, to provide anohmic contact with the base contact region 40 at a later stage.

In addition, in one embodiment, the p-base region 70 can be formedsimultaneously with an electrostatic discharge (ESD) process for ESDprotection during a CMOS transistor forming process. Thus, a separatemask would not be required when performing the fourth ion implantationprocess.

Then, a second heat treating process can be performed on thesemiconductor substrate 10 to activate the source and drain regions 30,the base contact region 40, the emitter contact region 50, and thecollector contact region 60.

According to embodiments of the present invention, an NPN bipolartransistor 100, can be formed of the emitter contact region 50, thep-base region 70, and the n-well 20.

The NPN bipolar transistor 100 including the p-base region 70 can helpincrease current gain compared to a PNP bipolar transistor.

Since electrons are majority carriers of the NPN bipolar transistor 100,better mobility is obtained versus a PNP bipolar transistor with holesas majority carriers. Thus, noise characteristics of the bipolartransistor 100 can be improved.

Also, by using the bipolar transistor 100 with superior flicker noisecharacteristics, the transistor can be used in a device with favorablephase noise characteristics of a voltage controlled oscillator (VCO)circuit.

Next, referring again to FIG. 6, an interlayer dielectric 80 includingcontacts 85 can be formed on the semiconductor substrate 10 includingthe nMOS transistor 35 and the NPN bipolar transistor 100.

The contacts 85 can be connected to the source and drain regions 30, thebase contact region 40, the emitter contact region 50, and the collectorcontact region 60, and can be formed in the interlayer dielectric 80.

The contacts 85 can be formed by any suitable process known in the art.For example, contact holes can be formed in the interlayer dielectric 80and filled with a metal material to form the contacts 85. The metalmaterial can be any suitable material known in the art, for exampletungsten (W).

Also, while not shown in the Figures, a metal wiring layer can be formedon the interlayer dielectric 80 including the contacts 85.

With the above-described semiconductor device and method of forming thesame according to embodiments of the present invention, a semiconductordevice formed of an nMOS transistor and an NPN bipolar transistor can beformed. An n-well, a p-base contact region, a base contact, an emittercontact, and a collector contact can be formed on a p-type semiconductorsubstrate with the nMOS transistor.

In one embodiment, source and drain regions of a pMOS transistor can besimultaneously formed with the base contact region, so that a separatemask would not required during ion implantation.

Also, according to certain embodiments, the emitter contact region andcollector contact region can be simultaneously formed with thesource/drain regions of the nMOS transistor, so that a separate maskwould not required during ion implantation.

Furthermore, in an embodiment, the p-base contact region can besimultaneously formed with an ESD process for ESD protection, such thata separate mask would not required during ion implantation.

Moreover, the p-type contact region can be lightly doped, to helpincrease current gain.

Additionally, because electrons are the majority carriers of the NPNbipolar transistor, superior mobility for better noise characteristicscan be achieved versus a PNP bipolar transistor with holes as majoritycarriers.

Also, by using a bipolar transistor with superior flicker noisecharacteristics, the semiconductor device can be used in a device suchas a voltage controlled oscillator (VCO) with favorable phase noisecharacteristics.

Any reference in this specification to “one embodiment,” “anembodiment,” “exemplary embodiment,” etc., means that a particularfeature, structure, or characteristic described in connection with theembodiment is included in at least one embodiment of the disclosure. Theappearances of such phrases in various places in the specification arenot necessarily all referring to the same embodiment. Further, when aparticular feature, structure, or characteristic is described inconnection with any embodiment, it is submitted that it is within thepurview of one skilled in the art to affect such feature, structure, orcharacteristic in connection with others of the embodiments.

Although embodiments have been described with reference to a number ofillustrative embodiments thereof, it should be understood that numerousother modifications and embodiments can be devised by those skilled inthe art that will fall within the spirit and scope of the principles ofthis disclosure. More particularly, various variations and modificationsare possible in the component parts and/or arrangements of the subjectcombination arrangement within the scope of the disclosure, the drawingsand the appended claims. In addition to variations and modifications inthe component parts and/or arrangements, alternative uses will also beapparent to those skilled in the art.

1. A semiconductor device, comprising: a semiconductor substrateincluding an n-well; an n-channel metal oxide semiconductor (nMOS)transistor on the semiconductor substrate separated from the n-well by adevice isolation layer; a p-base region on the n-well; a base contactregion and an emitter contact region on the p-base region; and acollector contact region on the n-well; wherein the emitter contactregion comprises n-type ions, the collector contact region comprisesn-type ions, the base contact region comprises p-type ions, and thep-base region comprises p-type ions.
 2. The semiconductor deviceaccording to claim 1, wherein the p-base region comprises p-type ions ata low concentration.
 3. The semiconductor device according to claim 1,wherein the emitter contact region is in electrical contact with thep-base region and the n-well to form an NPN bipolar transistor.
 4. Thesemiconductor device according to claim 3, further comprising adielectric on the nMOS transistor and the NPN bipolar transistor,wherein the dielectric comprises a contact connected to the base contactregion, a contact connected to the emitter contact region, and a contactconnected to the collector contact region.
 5. The semiconductor deviceaccording to claim 1, further comprising a thermal oxide layer betweenthe semiconductor substrate and the device isolation layer.
 6. Thesemiconductor device according to claim 1, wherein a depth of the p-baseregion is larger than a depth of the base contact region and a depth ofthe emitter contact region.
 7. The semiconductor device according toclaim 6, wherein the depth of the p-base region is smaller than a depthof the n-well.
 8. The semiconductor device according to claim 1, whereina concentration of the p-type ions of the base contact region is higherthan a concentration of the p-type ions of the p-base region.
 9. Amethod for manufacturing a semiconductor device, comprising: forming ann-well region on a semiconductor substrate; forming a gate on thesemiconductor substrate separated from the n-well region by a deviceisolation layer; forming a p-type base contact region on the n-wellregion; forming a source region and a drain region comprising n-typeions on the semiconductor substrate; forming an n-type emitter contactregion and n-type collector contact region on the n-well; and forming ap-type p-base region on the n-well including on the base contact regionand the emitter contact region.
 10. The method according to claim 9,wherein the p-base region comprises p-type ions at a low concentration.11. The method according to claim 9, wherein the gate, the sourceregion, and the drain region form an NMOS transistor on thesemiconductor substrate, and wherein the emitter contact region, thep-base region, and the n-well provide an NPN bipolar transistor.
 12. Themethod according to claim 11, further comprising forming a dielectricand contacts on the nMOS transistor and the NPN bipolar transistor. 13.The method according to claim 9, wherein forming the source region andthe drain region is performed simultaneously with forming the emittercontact region and the collector contact region using an ionimplantation process.
 14. The method according to claim 9, furthercomprising forming a thermal oxide layer between the semiconductorsubstrate and the device isolation layer.
 15. The method according toclaim 9, wherein the p-base region is formed to a depth greater thanthat of the base contact region and emitter contact region in then-well.
 16. The method according to claim 15, wherein the p-base regionis formed to a depth shallower than that of the n-well.
 17. The methodaccording to claim 9, wherein a concentration of the p-type ions of thebase contact region is higher than a concentration of the p-type ions ofthe p-base region.
 18. The method according to claim 9, furthercomprising heat treating the semiconductor substrate after forming thep-base region on the n-well.
 19. The method according to claim 9,further comprising forming a pMOS transistor.
 20. The method accordingto claim 19, wherein the forming of the base contact region issimultaneously performed with a process of forming a source and drainregion for the pMOS transistor.